The 2-D boundary element techniques for capacitance extraction of nanometer VLSI interconnects

摘要

This paper presents several techniques to accelerate the two-dimensional (2-D) direct boundary element method (BEM) for the capacitance extraction of nanometer very large-scale integrated interconnects. Among these techniques, the nonuniform discretization technique minimizes the number of unknowns needed for accurate computation. The technique of adding virtual dielectric interface increases the sparsity of the coefficient matrix. With the technique of blocked Gaussian elimination, the memory usage and CPU time for solving the linear equation system are largely reduced. The analytical primitive functions for the 2-D boundary integrals are also presented. Numerical results show that the presented techniques largely accelerate the 2-D boundary element method. And finally, our BEM-based capacitance solver demonstrates five times speedup over an advanced capacitance solver based on finite difference method. Copyright © 2013 John Wiley & Sons, Ltd.