DOUBLE PATTERNING METHOD FOR CREATING A REGULAR ARRAY OF PILLARS WITH DUAL SHALLOW TRENCH ISOLATION

摘要

A method is disclosed for forming vertical bipolar junction transistors including a regular array of base contact pillars and emitter contact pillars with a width below the minimum lithographical resolution F of the lithographic technique employed. In an embodiment, the pillar array features have a dimension of approximately F/2, though this dimension could be reduced down to other values compatible with embodiments of the invention. A storage element, such as a phase change storage element, can be formed above the regular array of base contact pillars and emitter contact pillars.