首页> 外国专利> METHOD FOR MANUFACTURING A VERTICAL SEMICONDUCTOR, CAPABLE OF PREVENTING A PILLAR FROM INCLINING BY NOT INCREASING AN ASPECT RATIO OF A VERTICAL GATE

METHOD FOR MANUFACTURING A VERTICAL SEMICONDUCTOR, CAPABLE OF PREVENTING A PILLAR FROM INCLINING BY NOT INCREASING AN ASPECT RATIO OF A VERTICAL GATE

机译:制造垂直半导体的方法,该方法能够通过不增加垂直门的纵横比来防止支柱倾斜

摘要

PURPOSE: A method for manufacturing a vertical semiconductor is provided to prevent an upper side of a pillar from being damaged due to the etching and etch back process by forming a hard mask pattern stacking a first hard mask nitride film, a hard mask poly film, and a second hard mask nitride film.;CONSTITUTION: A hard mask pattern(203) is formed on a silicon substrate(201). A pad oxide film(202), a first hard mask nitride film(203a), a second hard mask nitride film(203c) are formed on the silicon substrate. A photosensitive pattern to define a pillar region is formed by exposing and developing the photosensitive pattern. The pillar is formed by etching the silicon substrate using the hard mask pattern as the etching mask. A gate electrode is formed on the surface of the pillar. A surrounding gate electrode is formed by removing a gate electrode on the upper surface of the pillar.;COPYRIGHT KIPO 2010
机译:目的:提供一种垂直半导体的制造方法,通过形成堆叠第一硬掩模氮化物膜,硬掩模多晶硅膜的硬掩模图案,防止柱的上侧由于蚀刻和回蚀工艺而受到损坏,组成:第二硬掩模氮化物膜。构成:在硅衬底(201)上形成硬掩模图案(203)。在硅衬底上形成垫氧化膜(202),第一硬掩模氮化物膜(203a),第二硬掩模氮化物膜(203c)。通过曝光和显影感光图案来形成限定柱区域的感光图案。通过使用硬掩模图案作为蚀刻掩模来蚀刻硅基板来形成柱。在柱的表面上形成栅电极。通过去除柱子上表面的栅电极来形成周围的栅电极。; COPYRIGHT KIPO 2010

著录项

  • 公开/公告号KR20090116151A

    专利类型

  • 公开/公告日2009-11-11

    原文格式PDF

  • 申请/专利权人 HYNIX SEMICONDUCTOR INC.;

    申请/专利号KR20080041897

  • 发明设计人 KIM DO HYUNG;

    申请日2008-05-06

  • 分类号H01L29/78;H01L21/336;

  • 国家 KR

  • 入库时间 2022-08-21 18:34:04

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