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PAGE BUFFER OF A FLASH MEMORY DEVICE WHICH IMPROVES THE SPEED OF VERIFICATION AND READ OPERATIONS BY COUNTING POTENTIAL VARIATIONS OF A PRE-CHARGED SENSOR NODE, AND A READ OPERATION AND VERIFICATION OPERATION USING THE SAME
PAGE BUFFER OF A FLASH MEMORY DEVICE WHICH IMPROVES THE SPEED OF VERIFICATION AND READ OPERATIONS BY COUNTING POTENTIAL VARIATIONS OF A PRE-CHARGED SENSOR NODE, AND A READ OPERATION AND VERIFICATION OPERATION USING THE SAME
PURPOSE: A page buffer of a flash memory device and a read operation and verification operation using the same are provided to detect a failure state of each memory cell by outputting verification data per bit line instead of a page unit in the verification operation.;CONSTITUTION: A bit line selection part(210) comprises a plurality of NMOS transistors(N101-N104). A pre-charging unit(220) comprises a PMOS transistor(P101) connected between a voltage terminal and a sensor node. The PMOS transistor applies power voltage to the sensor node according to a pre-charge signal. A register(230) is connected between the sensor node and an input/output terminal. The register includes a latch for temporarily storing data. An output circuit(240) comprises a data signal generator(241) and a counter(242). The data signal generator comprises a capacitor, inverters and an NMOS transistor. The counter outputs a data value in a read operation by counting an enable frequency of an output signal. The counter outputs a pass signal or a fail signal by counting the enable frequency of the output signal in a verification operation.;COPYRIGHT KIPO 2010
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