Low-power, high write latency mode or a high-power, low write latency mode and / or memory device and method having a write latency selectable independently

摘要

Logic circuit operates write receivers in either one of dynamic random access memory device of the low-power mode, high write latency mode or a high-power mode, low write latency mode. A third signal indicating that the logic circuit comprises: a high-power, low write latency mode has been enabled if a represents the first signal, the second signal, the memory device is operating in a power down mode, the row of memory cells indicating that the activity in the memory device and the read transmitters in the memory device that receives the fourth signal indicates whether the activity. And a row of memory cells in a memory device active, every time the memory device is not operating in a power down mode, the read transmitters are not a active, the high-power, low write latency mode is to be enabled in the memory device, a logic circuit write receivers maintain the power for.; Low-power mode, high write latency mode, the high-power mode, low write latency mode, the power-down mode