首页> 外国专利> WAFER LEVEL CHIP SIZE PACKAGE OF A SEMICONDUCTOR DEVICE BY HOLE CONNECTION TO MINIMIZE THE LENGTH OF WIRING AND A MANUFACTURING METHOD THEREOF

WAFER LEVEL CHIP SIZE PACKAGE OF A SEMICONDUCTOR DEVICE BY HOLE CONNECTION TO MINIMIZE THE LENGTH OF WIRING AND A MANUFACTURING METHOD THEREOF

机译:通过孔连接来最小化接线长度的半导体装置的晶圆级晶片尺寸封装及其制造方法

摘要

PURPOSE: A wafer level chip size package of a semiconductor device by hole connection and a manufacturing method thereof are provided to prevent light loss and improve the sensitivity of the image sensor and image quality.;CONSTITUTION: A wafer level chip size package of a semiconductor device by hole connection comprises a substrate in which a plurality of semiconductor devices and an electrode pad are formed, a through hole which is formed in contact with the electronic pad on a dicing street, an insulating layer which is formed on the back side of the through hole and the substrate, a metal seed layer which is formed on the back side of the insulating layer and the substrate, a penetrating electrode which is formed on the top of the electrode pad and inside of the through hole, and a bump which is formed in the penetrating electrode.;COPYRIGHT KIPO 2010
机译:目的:提供一种通过孔连接的半导体器件的晶片级芯片尺寸封装及其制造方法,以防止光损失并提高图像传感器的灵敏度和图像质量。通过孔连接的器件包括:衬底,在衬底中形成多个半导体器件;以及电极垫;通孔,其形成为与切割道上的电子垫接触;绝缘层,其形成在切割路径的背面上。通孔和基板,在绝缘层和基板的背面上形成的金属籽晶层,在电极焊盘的顶部和通孔的内部形成的穿透电极,以及形成为凸点的凸点。在穿透电极中形成。; COPYRIGHT KIPO 2010

著录项

  • 公开/公告号KR20100005455A

    专利类型

  • 公开/公告日2010-01-15

    原文格式PDF

  • 申请/专利权人 PARK TAE SEOK;

    申请/专利号KR20080065493

  • 发明设计人 KIM YOUNG SUNG;PARK TAE SEOK;

    申请日2008-07-07

  • 分类号H01L23/48;H01L23/12;

  • 国家 KR

  • 入库时间 2022-08-21 18:33:31

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