首页> 外国专利> SEMICONDUCTOR DEVICE AND A METHOD FOR MANUFACTURING THE SAME, CAPABLE OF PREVENTING THE LATCH-UP OF AN INTEGRATED CIRCUIT WITHOUT A DOUBLE GUARD RING

SEMICONDUCTOR DEVICE AND A METHOD FOR MANUFACTURING THE SAME, CAPABLE OF PREVENTING THE LATCH-UP OF AN INTEGRATED CIRCUIT WITHOUT A DOUBLE GUARD RING

机译:半导体装置及其制造方法,能够防止在没有双重保护环的情况下对集成电路的闩锁

摘要

PURPOSE: A semiconductor device and a method for manufacturing the same are provided to form a first and a second latch-up prevention regions without an additional process by simultaneously performing a process for forming the latch-up prevention regions while the well of a low voltage transistor is formed.;CONSTITUTION: A first conductive well(110) is formed on a semiconductor substrate(100). Element isolation layers(120, 122, 124, 126, 128) are formed on the first conductive well. A gate pattern(150) is formed on the upper side of the first conductive well. Second drift regions are formed on the both side of the gate pattern. Second conductive source and drain regions are formed in the second conductive drift regions. A bias voltage is applied to pick-up regions(190, 192). Conductive latch-up prevention regions(140, 142) are formed on the lower side of the pick-up regions.;COPYRIGHT KIPO 2010
机译:目的:提供一种半导体器件及其制造方法,以通过在低电压阱的同时执行形成防闩锁区域的工艺来形成第一和第二防闩锁区域,而无需额外的处理组成:组成:第一导电阱(110)形成在半导体衬底(100)上。在第一导电阱上形成元件隔离层(120、122、124、126、128)。在第一导电阱的上侧形成栅极图案(150)。第二漂移区形成在栅极图案的两侧。在第二导电漂移区中形成第二导电源极和漏极区。向拾取区域(190、192)施加偏置电压。在拾取区域的下侧形成导电防闩锁区域(140、142)。;COPYRIGHT KIPO 2010

著录项

  • 公开/公告号KR20100049222A

    专利类型

  • 公开/公告日2010-05-12

    原文格式PDF

  • 申请/专利权人 DONGBU HITEK CO. LTD.;

    申请/专利号KR20080108304

  • 发明设计人 KIM SAN HONG;KIM JONG MIN;

    申请日2008-11-03

  • 分类号H01L29/78;H01L21/336;

  • 国家 KR

  • 入库时间 2022-08-21 18:32:48

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