首页> 外国专利> VERTICAL CHANNEL TRANSISTOR AND MANUFACTURING METHOD THEREOF HAVING THE DOUBLE GATE ELECTRODE SECURING THE CHANNEL LENGTH THROUGH THE VERTICAL CHANNEL

VERTICAL CHANNEL TRANSISTOR AND MANUFACTURING METHOD THEREOF HAVING THE DOUBLE GATE ELECTRODE SECURING THE CHANNEL LENGTH THROUGH THE VERTICAL CHANNEL

机译:垂直通道晶体管及其制造方法,其中双门电极通过垂直通道来确保通道长度

摘要

PURPOSE: A vertical channel transistor and the manufacturing method thereof having the double gate electrode are that the pillar the film for pillar is in filled is formed in the trench in which the sacrificing layer is etched and which is formed for pillar.;CONSTITUTION: The sacrificing layer(21) is formed on the substrate(20). A plurality of trench for pillars in which the sacrificing layer is etched and exposing substrate is formed. The film for pillar is in filled within the trench for pillar and a plurality of pillars(22) projected from substrate is formed. The sacrificing layer is eliminated and the sidewall of pillar exposes.;COPYRIGHT KIPO 2011
机译:用途:具有双栅电极的垂直沟道晶体管及其制造方法是在用于蚀刻牺牲层并形成柱的沟槽中形成填充有用于柱的膜的柱。牺牲层(21)形成在基板(20)上。形成多个用于柱的沟槽,其中牺牲层被蚀刻并且暴露基板。将用于支柱的膜填充在用于支柱的沟槽内,并且形成从基板突出的多个支柱(22)。牺牲层被消除,支柱的侧壁暴露出来。; COPYRIGHT KIPO 2011

著录项

  • 公开/公告号KR20100113721A

    专利类型

  • 公开/公告日2010-10-22

    原文格式PDF

  • 申请/专利权人 HYNIX SEMICONDUCTOR INC.;

    申请/专利号KR20090032170

  • 发明设计人 CHO HEUNG JAE;

    申请日2009-04-14

  • 分类号H01L29/78;H01L21/336;

  • 国家 KR

  • 入库时间 2022-08-21 18:31:42

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