This invention relates to a processing method and apparatus for implementing a systolic array-type structure. The input data is passed to the processing means (FU) for processing the input data based on the generated control signal from the pre-determined sequence to be stored, the instruction data (5) at a depth configurable register means (DCF), register means (DCF ) is the depth of the data is controlled in accordance with the instruction. Thus, the systolic array is no need to issue the operations clearly implement register move to implement the array of delay lines, for example, may be mapped to a programmable processor such as a VLIW processor.
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