SEMICONDUCTOR DEVICE HAVING A METAL GATE ELECTRODE FORMED ON AN ANNEALED HIGH-? GATE DIELECTRIC LAYER

摘要

A method of forming a transistor gate stack having an annealed gate dielectric layer is first separated by a trench, and starts by providing a substrate comprising a second spacer. Uniform high-k gate dielectric layer is deposited in the trench to a thickness in the range of from 3 to 60, and in the substrate. Next, a capping layer is formed on the high-k gate dielectric layer to fill the trench substantially, covers the high-k gate dielectric layer. Then, the high-k gate dielectric layer is annealed at a temperature over 600 . The capping layer is removed to expose an annealed high-k gate dielectric layer. Then, the metal layer is deposited on the annealed high-k gate dielectric layer. Removing excess material and can be a CMP process in order to complete the formation of the transistor gate stack used.