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A method for the production of transistors having epitaxial silicon - germanium for reduced contact resistance in the case of field effect transistors -

机译:一种用于制造具有外延硅锗晶体管的方法,以降低场效应晶体管的接触电阻

摘要

A method for the preparation of n - channel - and p - channel - transistors, wherein said method comprising the steps of:Form of recesses in a silicon substrate for source - and the drain - areas adjacent to the gate - structures for n - channel - and p - channel - transistors;Waxes of sige in the recesses, in order to source - and the drain - regions for the n - channel - and p - channel - transistors; andDegradation of voltage in channel - areas of the n - channel - transistors, which originates from the growth of the sige, without the voltage in channel - areas of the p - channel - transistors to substantially influence, wherein the stress in the n - channel - transistors is reduced by a dielectric material of isolation trenches is etched on one side of the source - region and a side of the drain - region of the n - channel - transistors are arranged.
机译:一种制备n沟道和p沟道晶体管的方法,其中所述方法包括以下步骤:在硅衬底中形成用于源极-和漏极-与栅极相邻的区域的凹槽-用于n-沟道的结构。 -和p-沟道-晶体管;凹槽中的蜡,以便为n-沟道-和p-沟道-晶体管提供源极-和漏极-区域;和沟道-n-沟道-晶体管区域中的电压的退化,这源于sige的增长,而沟道-p-沟道-晶体管区域中的电压基本上没有影响,其中n-沟道中的应力-通过在n-沟道-晶体管的源极-区域的一侧和漏极-区域的一侧上蚀刻隔离沟槽的介电材料来减少晶体管。

著录项

  • 公开/公告号DE112007000662B4

    专利类型

  • 公开/公告日2010-09-23

    原文格式PDF

  • 申请/专利权人

    申请/专利号DE20071100662T

  • 发明设计人

    申请日2007-03-29

  • 分类号H01L21/8238;H01L27/092;H01L21/336;

  • 国家 DE

  • 入库时间 2022-08-21 18:29:04

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