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SOI TRANSISTOR WITH SELF-ALIGNED MASS PLAN AND GRID AND VARIABLE THICKNESS OXIDE
SOI TRANSISTOR WITH SELF-ALIGNED MASS PLAN AND GRID AND VARIABLE THICKNESS OXIDE
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机译:具有自定质量计划和网格和可变厚度氧化层的SOI晶体管
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摘要
A self-aligned gate transistor (100) with a grid (116) and a ground plane (104a) comprising: - a semiconductor-based substrate (102); - a portion (104a) of organometallic material having a first face disposed thereon facing one side of the substrate, forming the ground plane of the transistor, - a dielectric layer (106) having a first face disposed against a second face of the portion of organometallic material opposite to the first face of the portion of material organometallic portions, - dielectric portions (120, 124) disposed between the face of the substrate and the first face of the dielectric layer, around the portion of organometallic material, a section, in a plane substantially parallel to the face of the substrate, of the gate of the transistor being substantially equal to a section of the portion of organometallic material in said plane.
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