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Cascode amplifier circuit and folded cascode amplifier circuit

机译:级联放大器电路和折叠级联放大器电路

摘要

To provide a cascode amplifying circuit having large amplifying gain without narrowing an output operational range or deteriorating response performance of the circuit even with a constitution by a small number of elements is achieved by applying negative feedback from the source to the gate of an MOS transistor M2 provided with an output terminal at the drain via the source and the drain of an MOS transistor M3 of N-channel type, the source and the drain of an MOS transistor M4 of P-channel type and a current mirror constituted by MOS transistors M5 and M6 of N-channel type. By this constitution, operation of the MOS transistor M3 is not effected with influence of lowering of voltage of the source of the MOS transistor M2, a wide output operational range is provided and mirror effect with respect to gate/drain capacitance of the MOS transistor is restrained to thereby restrain a reduction in response speed.
机译:通过提供从MOS晶体管M2的源极到栅极的负反馈,即使在元件数较少的情况下,也能够提供具有大的放大增益而不会使输出工作范围变窄或电路的响应性能变差的共源共栅放大电路。经由N沟道型的MOS晶体管M3的源极和漏极,P沟道型的MOS晶体管M4的源极和漏极以及由MOS晶体管M5和M构成的电流镜在漏极上具有输出端子。 N通道类型的M6。通过这种构造,MOS晶体管M3的操作不受MOS晶体管M2的源极的电压降低的影响,提供了宽的输出操作范围,并且相对于MOS晶体管的栅极/漏极电容具有镜像效应。限制从而限制响应速度的降低。

著录项

  • 公开/公告号JP4785243B2

    专利类型

  • 公开/公告日2011-10-05

    原文格式PDF

  • 申请/专利权人 セイコーNPC株式会社;

    申请/专利号JP20000357699

  • 发明设计人 宮部 悟;杉本 泰博;

    申请日2000-11-24

  • 分类号H03F1/22;H03K19/0944;

  • 国家 JP

  • 入库时间 2022-08-21 18:18:44

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