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Logic synthesis method and logic synthesis apparatus
Logic synthesis method and logic synthesis apparatus
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机译:逻辑综合方法及逻辑综合装置
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摘要
The present invention provides a logic-synthesis method and a logic synthesizer that can estimate the performance of an LSI circuit during the RTL-design phase. The logic-synthesis method includes the steps of generating a library having a buffer-tree-characteristic description, determining the position where the fanout value is high by analyzing a logic-design description, specifying the configuration of a buffer tree including the high fanout position, and performing logic synthesis according to the logic-design description.
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