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Non-volatile memory device and system having reduced bit line bias time
Non-volatile memory device and system having reduced bit line bias time
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机译:具有减少的位线偏置时间的非易失性存储装置和系统
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摘要
A non-volatile memory device and system are provided. The non-volatile memory device including; a memory cell array of memory blocks, and a bit line bias block connected to the bit lines and configured to precharge the bit lines, a page buffer precharging the plurality of bit lines and sensing data stored in the memory block via the bit lines, and a controller controlling the bit line bias block to simultaneously precharge the bit lines with the page buffer, thereby reducing the bit line bias time.
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