Semiconductor memory device realizing a channel voltage control scheme adopting dummy cells with threshold voltage higher than threshold voltage of erased memory cells and method thereof

摘要

A semiconductor memory device with NAND cell units arranged therein, the NAND cell unit including: a plurality of electrically rewritable and non-volatile memory cells connected in series; first and second select gate transistors disposed at the both ends of the NAND cell unit for coupling it to a bit line and a source line, respectively; and dummy cells disposed adjacent to the first and second select gate transistors in the NAND cell unit, wherein the dummy cells are set at a state with a threshold voltage higher than that of an erase state of the memory cell.