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2×VDD-tolerant logic circuits and a related 2×VDD-tolerant I/O buffer with PVT compensation
2×VDD-tolerant logic circuits and a related 2×VDD-tolerant I/O buffer with PVT compensation
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机译:具有PVT补偿的2×VDD耐受逻辑电路和相关的2×VDD耐受I / O缓冲器
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摘要
A 2×VDD-tolerant input/output (I/O) buffer circuit with process, voltage, and temperature (PVT) compensation suitable for CMOS technology is disclosed. A 2×VDD-tolerant I/O buffer with a PVT compensation circuit is implemented with novel 2×VDD-tolerant logic gates. Output slew rate variations can be kept within smaller ranges to match maximum and minimum timing specifications. A 2×VDD tolerant logic circuit for implementing the I/O buffer is also disclosed.
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