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Integrated circuit including built-in self test circuit to test memory and memory test method
Integrated circuit including built-in self test circuit to test memory and memory test method
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机译:包括用于测试存储器的内置自测试电路的集成电路和存储器测试方法
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摘要
An integrated circuit includes multiple memory circuits including memory cell arrays different in size, a BIST circuit which has a cell sequential transition test processor and which outputs a test cell address, a transition direction specification signal and an active signal. The integrated circuit has adjustment circuits which are provided respectively for the memory circuits and which replace the test cell address with the test cell address in a memory cell array area, or which convert the active signal into a signal indicating non-execution when the test cell address outputted from the BIST circuit corresponds to a cell in a virtual cell array being in an area outside the memory cell array.
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