Built-in self-test circuit for testing multiple embedded memory devices and integrated circuit including the same

摘要

PURPOSE: A BIST(Built In Self Test) circuit for testing multi-memory and an integrated circuit apparatus with the BIST circuit are provided to reduce the testing time to a plurality of memories by processing a testing with respect to each memory in parallel. CONSTITUTION: A BIST controller(310) generates test data for testing memories(331-333), inputs the test data to the memories(331-333), and compares read data to determine positive/negative of the memories(331-333). A plurality of multiplexers(321-323) transmit the test data to the memories(331-333) upon testing the memories(331-333) and transfer normal data to the memories(331-333) in a normal operation of the memories(331-333). Output selecting units(351-353) are connected to the memories(331-333) and a bus(390) to output the read data from the respective memories(331-333) in parallel to the BIST controller(310) upon testing the memories(331-333). The output selecting units(351-353) output the read data from the memories(331-333) to the bus(390) in the normal operation of the memories(331-333).