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Multiple bit upset insensitive error detection and correction circuit for field programmable gate array based on static random access memory blocks
Multiple bit upset insensitive error detection and correction circuit for field programmable gate array based on static random access memory blocks
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机译:基于静态随机存取存储块的现场可编程门阵列的多位不敏感错误检测与校正电路
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摘要
A method for detecting and correcting bit errors. The method includes the steps of receiving original data, partitioning the memory storage into a first portion and a second portion, storing the original data in the first portion of the memory buffer, modifying the original data into modified data, storing the modified data in the second portion of the memory buffer, comparing the original data with the modified data, combining the original data and the modified data to create a final data stream, and outputting the final data stream. The method may further include the step of calculating and storing parity data.
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