MATRIX INVERSION USING QR DECOPOSITION ON A PARALLEL PIPELINED SYSTOLIC ARRAY

摘要

The present invention refers to the field of wireless communications and more specifically to the design of a Parallel Pipelined Systolic Array (PPSA) architecture that implements a Multiple Input Multiple Output (&Mgr;&Igr;&Mgr;&Ogr;) zero-forcing detector. In particular the invention refers to a systolic array architecture that implements QR decomposition (QRD), i.e. a method for performing matrix inversion and an apparatus to implement such a method. The invention also refers to a receiving apparatus for Multiple Input Multiple Output transmission. An apparatus for QR decomposition of a matrix &EEgr; with at least four columns to an upper triangular R matrix and a unitary QH matrix according to the invention comprises at least four pipeline branches, whereby a) each one of the four pipeline branches implements a systolic array structure to process one of the at least four columns of the &EEgr; matrix and b) at least two of the at least four systolic array structures are different. A method for QR decomposition of a matrix &EEgr; with at least four columns to an upper triangular R matrix and a unitary Q matrix according to the invention, employes at least four systolic array pipeline branches that form a parallel pipelined systolic array architecture, whereby each one of the at least four columns of the &EEgr; matrix is processed by one of the at least four systolic array pipeline branches, the at least four columns of the &EEgr; matrix are processed in parallel by the at least four systolic array pipeline branches, and at least two of the at least four systolic array pipeline branches have a different structure.