BUFFER CIRCUIT HAVING REDUCED LEAKAGE CURRENT AND METHOD OF REDUCING LEAKAGE CURRENT IN A FIELD PROGRAMMABLE DEVICE

摘要

A technique for reducing leakage current in static CMOS devices by addingadditional transistors in series between selected inverters and ground orpower. NMOS and PMOS transistors are added to selected buffers comprised oftwo inverters in series. The PMOS transistor (124) is connected between thefirst inverter (112,114) and power (Vdd) and the NMOS transistor (126) isconnected between the second inverter (128) and ground. The added transistorsare controlled by a memory cell (130) to be on when the buffer is being usedand off when the buffer is unused. Alternatively, no PMOS transistor is addedand an existing PMOS transistor of the first inverter is manufactured to sitin a Vgg well. The same tech niques are employed with selected buffer pairs.