首页> 外国专利> SEMICONDUCTOR MEMORY DEVICE REDUCING THE RESISTANCE VARIATION OF A DATA TRANSMISSION LINE, CAPABLE OF COMPENSATING THE RESISTANCE VARIATION OF AN INTERCONNECTION

SEMICONDUCTOR MEMORY DEVICE REDUCING THE RESISTANCE VARIATION OF A DATA TRANSMISSION LINE, CAPABLE OF COMPENSATING THE RESISTANCE VARIATION OF AN INTERCONNECTION

机译:减少数据传输线电阻变化的半导体存储器,能够补偿互连电阻变化

摘要

PURPOSE: A semiconductor memory device reducing the resistance variation of a data transmission line are provided to make the resistance of a interconnection by combining a low resistance interconnection and high resistance interconnection to form a data transmission line.;CONSTITUTION: A second memory cell block(1b) is adjacent to a first memory cell block(1a) in a first direction. An interconnection rerouting unit is interposed between first and second memory cell blocks. The first memory cell block includes a plurality of first and second units and a plurality of interconnections. A first interconnection is connected to the end of the first cell unit respectively. The second interconnection is connected to the end of the second cell unit respectively.;COPYRIGHT KIPO 2011
机译:用途:一种半导体存储器件,通过组合低电阻互连和高电阻互连以形成数据传输线来减小数据传输线的电阻变化,以形成互连的电阻;组成:第二个存储单元块( 1b)在第一方向上与第一存储单元块(1a)相邻。互连重新路由单元介于第一和第二存储单元块之间。第一存储单元块包括多个第一单元和第二单元以及多个互连。第一互连分别连接到第一电池单元的末端。第二个互连分别连接到第二个单元的末端。; COPYRIGHT KIPO 2011

著录项

  • 公开/公告号KR20110046259A

    专利类型

  • 公开/公告日2011-05-04

    原文格式PDF

  • 申请/专利权人 KABUSHIKI KAISHA TOSHIBA;

    申请/专利号KR20100088287

  • 发明设计人 NOGUCHI MITSUHIRO;

    申请日2010-09-09

  • 分类号G11C16/34;G11C16/08;G11C16/24;

  • 国家 KR

  • 入库时间 2022-08-21 17:52:03

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