首页> 外国专利> METHOD FOR FORMING TRIPLE GATE OF SEMICONDUCTOR DEVICE AND TRIPLE GATE OF SEMICONDUCTOR FOR THE SAME

METHOD FOR FORMING TRIPLE GATE OF SEMICONDUCTOR DEVICE AND TRIPLE GATE OF SEMICONDUCTOR FOR THE SAME

机译:形成半导体器件的三重栅极的方法和用于同一器件的三重栅极的形成方法

摘要

PURPOSE: A method for forming a triple gate of a semiconductor device is provided to improve the characteristics and reliability of the device without damage due to plasma, by forming a trench through a vapor etching process. CONSTITUTION: A buffer layer and a hard mask are formed on a substrate. A hard mask pattern(104A) and a buffer layer pattern(102A) are formed by etching the hard mask and the buffer layer. A first and a second trench(108) are formed within the substrate by performing a vapor etching process using the hard mask pattern as an etch barrier layer. A filling insulation layer is formed to bury the first and the second trench. The hard mask pattern and the buffer layer pattern are removed. A gate insulating layer is formed on the substrate between the first and the second trench. A conductive film is formed to cover the gate insulating layer. A gate electrode is formed by etching the conductive film.
机译:目的:提供一种用于形成半导体器件的三重栅极的方法,以通过通过气相蚀刻工艺形成沟槽来改善器件的特性和可靠性而不会由于等离子体造成损坏。组成:在基板上形成缓冲层和硬掩模。通过蚀刻硬掩模和缓冲层来形成硬掩模图案(104A)和缓冲层图案(102A)。通过使用硬掩模图案作为蚀刻阻挡层执行气相蚀刻工艺,在基板内形成第一沟槽(108)和第二沟槽(108)。形成填充绝缘层以掩埋第一沟槽和第二沟槽。去除硬掩模图案和缓冲层图案。在第一沟槽和第二沟槽之间的衬底上形成栅绝缘层。形成导电膜以覆盖栅极绝缘层。通过蚀刻导电膜来形成栅电极。

著录项

  • 公开/公告号KR101016349B1

    专利类型

  • 公开/公告日2011-02-22

    原文格式PDF

  • 申请/专利权人

    申请/专利号KR20080054886

  • 发明设计人 차한섭;

    申请日2008-06-11

  • 分类号H01L21/336;H01L29/78;

  • 国家 KR

  • 入库时间 2022-08-21 17:50:33

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