Memory sram cell of a transistor integrated on several levels, and the threshold voltage vt is adjustable dynamically

摘要

The present invention relates to a cell of ram not - volatile at random access, comprising, on a substrate surmounted by a stack of layers, - a first plurality of transistors located at a given level of the stack of which at least a first access transistor (have) and at least one second access transistor (mar) disposed respectively between a first bit line (bll) and a first storage node (l), and a second bit line (lrl) and a second storage node (r) the first access transistor and the second access transistor having a gate connected to a word line (wl), - a second plurality of transistors (ml 1, the mlr, md, overexpression) forming a lever and located at least one other level of the stack less than the given level, the transistors of the second plurality of transistors (ml 1, the mlr, md, overexpression) comprise a gate electrode situated in front of a channel region of a transistor of the second plurality of transistors (absent, tue) and separated from the channel region by means of an insulating zone designed to allow a coupling between the gate electrode and the channel region.