首页> 外国专利> The non-defective chip classification method in wafer, chip quality determination method using the same, as well as chip classification program, chip quality judgment program, the production method of marking mechanism and semiconductor device

The non-defective chip classification method in wafer, chip quality determination method using the same, as well as chip classification program, chip quality judgment program, the production method of marking mechanism and semiconductor device

机译:晶片中的无缺陷芯片分类方法,使用该方法的芯片质量确定方法,以及芯片分类程序,芯片质量判断程序,标记机构的制造方法和半导体装置

摘要

PROBLEM TO BE SOLVED: To sort a good quality chip with the consideration for concern for the degree of quality degradation in the result of wafer test of a wafer, where multiple chips are disposed into a matrix form in X-axis direction and Y-axis direction.;SOLUTION: On the basis of a wafer test (S1), a defect chip is sorted to the defect group so that neighboring defect chips belong to the same group (S2); when the number of the defect chips belonging to the defect group is the prescribed threshold of the number of the defect chips, the defect group is decided as being in a distribution of concentrated defects (S3); the peripheral region of the distribution of concentrated defects, including all defect chips belonging to the defect group and nondefective chips in the periphery is set in a specific range (S4), and nondefective chips in the peripheral range of the distribution of concentrated defects are decided as being chips to be evaluated. For every objective chip, the number of directions in which the defect chips, belonging to the distribution of concentrated defects are present, is counted in the 4 directions in X-axis direction and Y-axis direction; and according to the number of directions, the objective chip is sorted to a plurality of chip indexes (S5).;COPYRIGHT: (C)2009,JPO&INPIT
机译:解决的问题:在对晶片进行晶片测试时,考虑到质量下降的程度,对高质量的芯片进行分类,其中将多个芯片在X轴方向和Y轴上排列成矩阵形式解决方案:基于晶片测试(S1),将缺陷芯片分类到缺陷组中,以便相邻的缺陷芯片属于同一组(S2)。当属于缺陷组的缺陷芯片的数量是缺陷芯片的数量的规定阈值时,确定缺陷组为集中缺陷的分布(S3);将集中缺陷分布的外围区域(包括属于缺陷组的所有缺陷芯片和周围的非缺陷芯片)设置在特定范围内(S4),并确定集中缺陷分布的外围范围内的无缺陷芯片作为要评估的筹码。对于每个目标芯片,在X轴方向和Y轴方向上的4个方向上计数存在缺陷芯片的方向的数量,该缺陷芯片属于集中缺陷的分布。并根据方向数将目标芯片分类为多个芯片索引(S5)。版权所有:(C)2009,JPO&INPIT

著录项

  • 公开/公告号JP4931710B2

    专利类型

  • 公开/公告日2012-05-16

    原文格式PDF

  • 申请/专利权人 株式会社リコー;

    申请/专利号JP20070172725

  • 发明设计人 柳井 裕和;

    申请日2007-06-29

  • 分类号H01L21/66;

  • 国家 JP

  • 入库时间 2022-08-21 17:39:56

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