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From the transistor null principal plane and the aforementioned principal plane which possess the dielectric stressor element in the depth which differs, from the semiconductor
From the transistor null principal plane and the aforementioned principal plane which possess the dielectric stressor element in the depth which differs, from the semiconductor
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机译:从晶体管的零位主平面和上述主平面具有与半导体不同深度的介电应力源元件
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摘要
A chip is provided which includes an active semiconductor region and a field effect transistor ("FET") having a channel region, a source region and a drain region all disposed within the active semiconductor region. The FET has a longitudinal direction in a direction of a length of the channel region, and a transverse direction in a direction of a width of the channel region. A buried dielectric stressor element has a horizontally extending upper surface at a first depth below a major surface of a portion of the active semiconductor region, such as an east portion of the active semiconductor region. A surface dielectric stressor element is disposed laterally adjacent to the active semiconductor region at the major surface of the active semiconductor region. The surface dielectric stressor element extends from the major surface to a second depth not substantially greater than the first depth. The stresses applied by the buried and surface dielectric stressor elements cooperate together to apply a shear stress to the channel region of the FET.
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