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HIGH RESOLUTION, LOW POWER DESIGN FOR CPRI/OBSAI LATENCY MEASUREMENT
HIGH RESOLUTION, LOW POWER DESIGN FOR CPRI/OBSAI LATENCY MEASUREMENT
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机译:用于CPRI / OBSAI延迟测量的高分辨率,低功耗设计
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摘要
As part of the protocol for Common Public Radio Interface/Open Base Station Architecture Initiative (CPRI/OBSAI) systems, timing circuits are used to calculate the “round trip” latency across CPRI/OBSAI links. Traditionally, these timing circuits have been plagued with numerous problems. Here, however, a timing circuit is provided that has improved latency measurement accuracy, reduced power consumption, and a reduced likelihood of detecting a false comma. This is generally accomplished through the use of double edge latching in combination with post processing circuit and single bit transmission between low and high speed clock domains.
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