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Structure for detecting clock gating opportunities in a pipelined electronic circuit design

机译:用于检测流水线电子电路设计中的时钟门控机会的结构

摘要

A design structure for a pipeline electronic processor device may be embodied in a machine readable medium for designing, manufacturing or testing a processor integrated circuit. The design structure may embody a pipeline electronic circuit that enables power conservation in the stages of the pipeline via a simulation that identifies clock-gating opportunities among the stages of the pipeline. In one embodiment, simulation results assist a designer in the design of the pipeline electronic circuit design structure to achieve power conservation by incorporating clock-gating circuitry among the stages of the pipeline at clock gating opportunity locations that the simulation identifies.
机译:用于管线电子处理器设备的设计结构可以体现在用于设计,制造或测试处理器集成电路的机器可读介质中。该设计结构可以体现为流水线电子电路,该电路电子电路通过识别流水线各级之间的时钟门控机会的仿真来实现流水线各级中的功率节省。在一个实施例中,仿真结果通过在仿真所识别的时钟选通机会位置处的流水线的各级之间并入时钟选通电路,来帮助设计者设计流水线电子电路设计结构以实现功率节省。

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