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Speeding up Pipelined Circuits through a Combination of Gate Sizing and Clock Skew Optimization

机译：通过门限大小和时钟偏差优化相结合来加速流水线电路

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Harsha Sathyamurthy; Sachin S. Sapatnekar; John P. Fishburn;
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年度 1995
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1. Speeding up pipelined circuits through a combination of gate sizing and clock skew optimization [J] . Sathyamurthy H., Sapatnekar S.S. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems . 1998,第2期

机译：通过结合选通大小和时钟偏移优化来加速流水线电路
2. Synthesis of Dual-Mode Circuits Through Library Design, Gate Sizing, and Clock-Tree Optimization [J] . Kim Sangmin, Kang Seokhyeong, Shin Youngsoo ACM Transactions on Design Automation of Electronic Systems . 2016,第3期

机译：通过库设计，门控大小确定和时钟树优化来合成双模式电路
3. A CAD-Based Investigation of Clock-Skew Hazards in Pipelined NORA Dynamic Logic Circuits [J] . FEI YUAN Analog Integrated Circuits and Signal Processing . 2004,第1期

机译：基于CAD的流水线NORA动态逻辑电路中时钟偏斜危害的调查
4. Speeding up pipelined circuits through a combination of gate sizing and clock skew optimization [C] . Sathyamurthy, H., Sapatnekar, . 1995

机译：通过结合门径和时钟偏斜优化来加速流水线电路
5. Power and Timing Driven Optimal Gate, Clock Buffer and Clock Wire Sizing in High Performance Digital Integrated Circuits [D] . Farshidi, Amin. 2016

机译：功率和定时驱动最佳栅极，时钟缓冲器和时钟线寸在高性能数字集成电路中尺寸
6. Erratum: The combination of the functionalities of feedback circuits is determinant for the attractors’ number and size in pathway-like Boolean networks [O] . Eugenio Azpeitia, Stalin Muñoz, Daniel González-Tokman, -1

机译：勘误表：反馈电路的功能组合决定了类似路径的布尔网络中吸引子的数量和大小
7. A unified algorithm for gate sizing and clock skew optimization to minimize sequential circuit area [O] . Weitong Chuang, Sachin S Sapatnekar, Ibrahim N Hajj 1993

机译：栅极大小和时钟偏斜优化的统一算法，可最大程度地减少时序电路面积

Speeding up Pipelined Circuits through a Combination of Gate Sizing and Clock Skew Optimization

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