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Apparatus and method for clock signal synchronization in JTAG testing in systems having selectable modules processing data signals at different rates
Apparatus and method for clock signal synchronization in JTAG testing in systems having selectable modules processing data signals at different rates
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机译:在具有可选模块以不同速率处理数据信号的系统中,用于JTAG测试中时钟信号同步的设备和方法
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摘要
In a test and debug system in which a plurality of selectable modules under test have different operational rates, a selection unit associated with each module is used to control the application of the RCLK signal from the module to the combiner unit, the combiner unit providing a composite RCLK signal. Each selection unit has output signals of RCLK_NE and RCLK_PE signals which are applied to an combiner unit to form the composite RCLK signal. In response to the SELECT signal, the RCLK_NE and RCLK_PE are synchronized with the module RCLK signal. When the SELECT signal is removed, the RCLK_NE and RCLK_PE signals are continuously applied to the combiner unit.
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