首页>
外国专利>
Apparatus and method for clock signal synchronization in JTAG testing in systems having modules processing clock signals at different rates
Apparatus and method for clock signal synchronization in JTAG testing in systems having modules processing clock signals at different rates
展开▼
机译:在具有以不同速率处理时钟信号的模块的系统中,在JTAG测试中用于时钟信号同步的设备和方法
展开▼
页面导航
摘要
著录项
相似文献
摘要
In a test and debug system in which a plurality of modules under test have different operational rates, the system clock and the return clock signals from the modules lose synchronism. An error signal is produced when the clock signal makes a transition to a logic state that is the same logic state of the return clock signal of all of the modules. Apparatus is provided for generating logic signals when all of the return clock signals are in the same logic state. Two logic states are possible for all the return clock signals. A current state is latched until all the return clock signals are in the other state, at which time the second logic signal state is latched. The apparatus can be reset by an external signal.
展开▼