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Data processing system with branch target addressing using upper and lower bit permutation
Data processing system with branch target addressing using upper and lower bit permutation
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机译:具有使用高位和低位置换的分支目标寻址的数据处理系统
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摘要
A data processor or a data processing system used in compatible modes among which the number of bits of an address specifying a logical address space varies at the time of referring to a branch address table by extension of displacement of a branch instruction. At the time of generating a branch address of a first branch instruction, the data processor or the data processing system optimizes a multiple with which a displacement is multiplied in accordance with the number of bits of an address specifying a logical address space, adds extended address information to the value of a register, and refers to a branch address table with address information obtained by the addition. The referred information is used as a branch address. A multiple with which the displacement is multiplied can be changed in accordance with the mode.
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