System and method for dynamically switching between low and high frequency reference clock to PLL and minimizing PLL output frequency changes

摘要

A circuit is provided for use with a clock having an input divider portion, a feedback divider portion, a phase detector portion, a loop compensation filter portion and a voltage controlled oscillator portion. The input divider portion receives a reference signal and outputs a divided reference signal. The feedback divider portion receives an output signal from the circuit and outputs a divided feedback signal. The phase detector portion outputs a phase detector signal based on the divided reference signal and the divided feedback signal. The loop compensation filter portion outputs a tuning signal based on the phase detector signal. The voltage controlled oscillator portion output the outputs a signal based on the tuning signal. The phase detector portion changes the phase detector signal based on the input divider portion receiving the control signal and the feedback divider portion receiving the control signal.