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Void sealing in a dielectric material of a contact level of a semiconductor device comprising closely spaced transistors
Void sealing in a dielectric material of a contact level of a semiconductor device comprising closely spaced transistors
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机译:介电材料中的空隙密封,包括紧密排列的晶体管的半导体器件的接触面
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摘要
In sophisticated semiconductor devices, a contact structure may be formed on the basis of a void positioned between closely spaced transistor elements wherein disadvantageous metal migration along the void may be suppressed by sealing the voids after etching a contact opening and prior to filling in the contact metal. Consequently, significant yield losses may be avoided in well-established dual stress liner approaches while, at the same time, superior device performance may be achieved.
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