The integrated circuit includes memory cells (MC) with magnetoresistive memory effect. A matrix-shaped memory cell field (1) has bit lines (BL) and word lines (WL). The memory cells are connected between respective bit lines and respective word lines. The bit lines are connected to respective sense amplifiers (2) for reading a data signal from a corresponding memory cell. The sense amplifier comprises a fed-back operational amplifier (3) which supplies an output signal (OUT). A first control input (31) of the operational amplifier is connected with one of the bit liens. A capacitor is connected between a second control input (32) of the operational amplifier and ground (GND).
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