Highly reliable low-cost structure for wafer-level ball grid array packaging

摘要

Methods, systems, and apparatuses for wafer-level integrated circuit (IC) packages are described. An IC package includes an IC chip (702a), an insulating layer (1502) on the IC chip, a plurality of vias (1504a), a plurality of routing interconnects (1506a), and a plurality of bump interconnects (1512a). The IC chip has a plurality of terminals configured in an array on a surface of the IC chip. A plurality of vias through the insulating layer provide access to the plurality of terminals. Each of the plurality of routing interconnects has a first portion (1508) and a second portion (1510). The first portion of each routing interconnect is in contact with a respective terminal (604) of the plurality of terminals though a respective via, and the second portion of each routing interconnect extends over the insulating layer. Each bump interconnect of the plurality of bump interconnects is connected to the second portion of a respective routing interconnect of the plurality of routing interconnects whereby the insulating layer provides stress absorption with regard to stress applied to bump interconnect (1512a).