首页> 外国专利> VERTICAL TYPE SEMICONDUCTOR DEVICE CAPABLE OF REDUCING OPERATING ERRORS ACCORDING TO MISALIGNMENT OF CONTACTS, AND A MANUFACTURING METHOD THEREOF

VERTICAL TYPE SEMICONDUCTOR DEVICE CAPABLE OF REDUCING OPERATING ERRORS ACCORDING TO MISALIGNMENT OF CONTACTS, AND A MANUFACTURING METHOD THEREOF

机译:能够减少由于接触不良引起的操作误差的垂直型半导体装置及其制造方法

摘要

PURPOSE: A vertical type semiconductor device and a manufacturing method thereof are provided to reduce contact failure of a bit line contact by multiplying process margins when forming a bit line contact.;CONSTITUTION: A sacrificing film and inter-layer insulating films(106a-106f) are repeatedly laminated on a substrate(100). A semiconductor pattern(112) projected to the upper side of the inter-layer insulating film is formed inside a first opening part. A second opening part which exposes the substrate surface is formed between semiconductor patterns. A groove is formed by selectively eliminating the sacrificing film. A gate structure of multi-layer is formed within the groove. The gate structure is composed of a turner insulating layer(120a), a charge trapping layer(120b), a blocking dielectric layer(120c), and a control gate electrode(122).;COPYRIGHT KIPO 2012
机译:目的:提供一种垂直型半导体器件及其制造方法,以通过在形成位线接触时增加工艺裕量来减少位线接触的接触故障。组成:牺牲膜和层间绝缘膜(106a-106f) )被重复地层压在衬底(100)上。突出到层间绝缘膜的上侧的半导体图案(112)形成在第一开口部分的内部。在半导体图案之间形成露出基板表面的第二开口部。通过选择性地去除牺牲膜来形成凹槽。在凹槽内形成多层的栅极结构。栅极结构由转向绝缘层(120a),电荷俘获层(120b),阻挡介电层(120c)和控制栅电极(122)组成。; COPYRIGHT KIPO 2012

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