Low Voltage Regulated Cascade Circuits and CMOS Analog Circuits

摘要

Low-Voltage regulator Federated cascode circuit is disclosed. Circuit of the present invention is applied to the first current source and the bias voltage , the output terminal and the first MOS transistor , a gate coupled between a first node coupled between the first power supply terminal and the output terminal in order to achieve the object of the present invention and a second MOS transistor connected between the first node and the second power supply terminal , between the first and the third MOS transistor connected between a power supply terminal and the gate of the first MOS transistor , the gate of the first MOS transistor and the second power supply voltage a second current source connected to . Therefore , maintaining a high output resistance, and a large voltage swing width in a low voltage of 1V or less , while it is possible to maintain the stable operating characteristics .