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Electronic chip, has set of connection pillars electrically connected with vias, where pillars form protuberant regions relative to substrate and are provided with portion embedded in housing formed in thickness of substrate
Electronic chip, has set of connection pillars electrically connected with vias, where pillars form protuberant regions relative to substrate and are provided with portion embedded in housing formed in thickness of substrate
The chip has a semiconductor substrate (1) i.e. wafer, comprising interconnection vias (30) opening onto one face of the substrate. A set of connection pillars (35) is electrically connected with the vias. The pillars form protuberant regions relative to the substrate to receive an electrical contact. The pillars are provided with a portion (39) embedded in a housing formed in the thickness of the substrate, and depth of the housing is provided between 20 and 40 percent of height of the pillars. An independent claim is also included for a method for manufacturing an electronic chip.
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