首页> 外国专利> Electronic chip, has set of connection pillars electrically connected with vias, where pillars form protuberant regions relative to substrate and are provided with portion embedded in housing formed in thickness of substrate

Electronic chip, has set of connection pillars electrically connected with vias, where pillars form protuberant regions relative to substrate and are provided with portion embedded in housing formed in thickness of substrate

机译:电子芯片,具有与通孔电连接的一组连接柱,其中柱形成相对于基板的隆起区域,并且设有嵌入在壳体中的,以基板厚度形成的部分

摘要

The chip has a semiconductor substrate (1) i.e. wafer, comprising interconnection vias (30) opening onto one face of the substrate. A set of connection pillars (35) is electrically connected with the vias. The pillars form protuberant regions relative to the substrate to receive an electrical contact. The pillars are provided with a portion (39) embedded in a housing formed in the thickness of the substrate, and depth of the housing is provided between 20 and 40 percent of height of the pillars. An independent claim is also included for a method for manufacturing an electronic chip.
机译:该芯片具有半导体衬底(1),即晶片,其包括在衬底的一个表面上开口的互连通孔(30)。一组连接柱(35)与通孔电连接。柱相对于基板形成突出区域以接收电接触。支柱具有嵌入在以基板的厚度形成的壳体中的部分(39),并且壳体的深度设置在支柱的高度的20%至40%之间。还包括用于制造电子芯片的方法的独立权利要求。

著录项

  • 公开/公告号FR2969381A1

    专利类型

  • 公开/公告日2012-06-22

    原文格式PDF

  • 申请/专利权人 STMICROELECTRONICS (CROLLES 2) SAS;

    申请/专利号FR20100060980

  • 发明设计人 CHAPELON LAURENT-LUC;

    申请日2010-12-21

  • 分类号H01L23/538;H01L21/02;

  • 国家 FR

  • 入库时间 2022-08-21 17:04:06

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