Existing OOFDM systems use a single adaptive modulator whose output is then serial to parallel (S/P)converted before being supplied to the IFFT, cyclic prefix insertion and parallel/serial (P/S) conversion (see Fig. 1). This arrangement results in capacity limitations due to the maximum clock speed of the FPGA/ASIC used to implement the transmitter/receiver. The invention replaces the single adaptive modulator with multiple parallel adaptive modulators positioned after the S/P converter, thereby allowing each to be clocked at a lower rate. Additionally incoming data streams are padded out to a fixed data size/width which is fed into the S/P converter. The adaptive modulators are equipped with bus width converters (Fig. 3) which can strip out padding bits as required for the modulation scheme they are operating. This allows the transmitter/receiver operation to be decoupled from changes to the data rate/format. Receivers operate a mirror scheme in which the modulators add padding bits which are removed after P/S conversion.
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