A static CMOS flip-flop with low power consumption

摘要

An edge-triggered flip-flop comprises a cross-coupled latch which is set or reset by transistors 317 or 323 on the rising edge of the clock 330. The transistor 323 is enabled only if the data input is high and the output Q is low, and the transistor 317 is enabled only if the data input is low and the output Q is high. No internal nodes change state during clock cycles in which the data input is unchanged. Only three transistor gates are driven by the clock. The transistor 312 need be driven only occasionally by the clock signal 332, which may for example be active only once in every 100 cycles of the clock 330.