CMOS STANDARD CELL STRUCTURE WITH LOWER DATA DEPENDENCE OF THE STATIC POWER CONSUMPTION

摘要

The PMOS block (104) is connected between the virtual supply node (102) and output (101). The NMOS block (105) is connected between the virtual ground node (103) and output (101). The input of the balancing inverter chain (200, 300, 400) is connected to the output O (101). The balancing inverter chain is composed of at least one inverter and the output of the chain is the output (Y) of the structure. The static CMOS circuit (100) is supplemented with any combination of the following circuits. The virtual supply node (102) is connected to the supply rail by a serial P-type transistor (111), which gate (G), is connected to the ground rail. The virtual ground node (103) is connected to the ground rail by the serial N-type transistor (112), which gate (G) is connected to the supply rail. The virtual supply node (102) is connected to the output (101) by the complementary P-type transistor (121). The virtual ground node (103) is connected to the output (101) by the N-type complementary transistor (122).