OOR test pattern insertion circuit and OOR test pattern insertion method

摘要

PROBLEM TO BE SOLVED: To provide a pattern insertion circuit for OOR testing for causing disturbance of LM, for confirming that a reception side correctly detects and releases OOR.;SOLUTION: The pattern insertion circuit for OOR testing includes: a code inversion part 32 which, with OTU3 frame data DT₀-DT₃ being inputted, inverts one bit (a₀) among the LM arranged at bottom two bits (a₁a₀) being the representation of MFAS in binary format, to (r₀); an alarm pattern generating part 33 which replaces the other bit (a₁) of the LM with the data (b₁) of code (0) or code (1) so that repetition of identical code is four times or less, and (r₀) from the code inversion part 32 is arranged at one bit, for generating a pattern (b₁r₀) for OOR testing of 2 bit; and an alarm pattern insertion part 34 which replaces an LM of arbitrary lane with the pattern for ORR testing that is generated by the alarm pattern generating part 33.;COPYRIGHT: (C)2012,JPO&INPIT