首页> 外国专利> Implementing vertical die stacking to distribute logical function over multiple dies in through-silicon-via stacked semiconductor device

Implementing vertical die stacking to distribute logical function over multiple dies in through-silicon-via stacked semiconductor device

机译:在通过硅通孔堆叠的半导体器件中实现垂直管芯堆叠以在多个管芯上分配逻辑功能

摘要

A method and circuit for implementing die stacking to distribute a logical function over multiple dies, die identification and sparing in through-silicon-via stacked semiconductor devices, and a design structure on which the subject circuit resides are provided. Each die in the die stack includes predefined functional logic for implementing a respective predefined function. The respective predefined function is executed in each respective die and a respective functional result is provided to an adjacent die in the die stack. Each die in the die stack includes logic for providing die identification. An operational die signature is formed by combining a plurality of selected signals on each die. A die signature is coupled to a next level adjacent die using TSV interconnections where it is combined with that die signature.
机译:提供了一种用于实现管芯堆叠以在多个管芯上分配逻辑功能,通过硅通孔堆叠的半导体器件中的管芯识别和备用的方法和电路,以及提供本发明电路所驻留的设计结构。管芯堆叠中的每个管芯包括用于实现相应的预定义功能的预定义功能逻辑。在每个相应的管芯中执行相应的预定义功能,并且将相应的功能结果提供给管芯堆叠中的相邻管芯。管芯堆叠中的每个管芯包括用于提供管芯识别的逻辑。通过在每个芯片上组合多个选择的信号来形成可操作的芯片签名。管芯签名使用TSV互连耦合到邻近管芯的下一级,在这里它与该管芯签名结合在一起。

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