Die stacking is widely adopted for high chip count systems to reduce the requirement of substrate area. The incorporation of Through-Silicon-Via (TSV) as vertical interconnects further reduces the interconnect path length from the top die to substrate. As the fabrication resolution keeps on shrinking, devices of even higher chip count are required to be assembled in a single package, which results in even longer 3D interconnects. As such, accurate modelling of high speed interconnects is essential for the high frequency systems. In this work, 3D modelling and Full wave EM simulation were performed on the interconnect path which consists of TSV, metal re-distribution Layer (RDL) and bumps. Effect of the different number of die stack was analyzed based on the simulation results.
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