Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with at least two different gate level feature extensions beyond contact

摘要

A semiconductor device includes a substrate having a plurality of diffusion regions defined therein to form first and second p-type diffusion regions, and first and second n-type diffusion regions, with each of these diffusion regions electrically connected to a common node. The first p-type active area and the second p-type active area are contiguously formed together. The first n-type active area and the second n-type active area are contiguously formed together. Gate electrodes are formed from conductive features that are each defined within any one gate level channel. Each gate level channel is uniquely associated with and defined along one of a number of parallel oriented gate electrode tracks. A first PMOS transistor gate electrode is electrically connected to a second NMOS transistor gate electrode, and a second PMOS transistor gate electrode is electrically connected to a first NMOS transistor gate electrode.