Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with at least two different gate level features inner extensions beyond gate electrode

摘要

First and second p-type diffusion regions, and first and second n-type diffusion regions are formed in a semiconductor device. Each diffusion region is electrically connected to a common node. Gate electrodes are formed from conductive features that are each defined within any one gate level channel that is uniquely associated with and defined along one of a number of parallel gate electrode tracks. The first and second p-type diffusion regions are formed in a spaced apart manner relative to the first parallel direction, such that no single line of extent that extends across the substrate perpendicular to the first parallel direction intersects both the first and second p-type diffusion regions. At least a portion of the first n-type diffusion region and at least a portion of the second n-type diffusion region are formed over a common line of extent that extends across the substrate perpendicular to the first parallel direction.