首页> 外国专利> Methods of fabricating a dual polysilicon gate and methods of fabricating a semiconductor device using the same

Methods of fabricating a dual polysilicon gate and methods of fabricating a semiconductor device using the same

机译:制造双多晶硅栅极的方法和使用该双多晶硅栅极的半导体器件的制造方法

摘要

A dual polysilicon gate is fabricated by, inter alia, forming a polysilicon layer doped with impurities of a first conductivity type on a substrate having a first region and a second region, forming a mask pattern that covers the polysilicon layer in the first region and leaves the polysilicon layer in the second region, injecting impurities of a second conductivity type into the polysilicon layer in the second region left exposed by the mask pattern. Removing the mask pattern, and patterning the polysilicon layer to form a first polysilicon pattern in the first region and a second polysilicon pattern in the second region. The second polysilicon pattern is formed to have protrusions that laterally protrude from sidewalls thereof. Subsequently, impurities of the second conductivity type are injected into the substrate in the second region and into the protrusions of the second polysilicon pattern.
机译:通过在具有第一区域和第二区域的基板上形成掺杂有第一导电类型的杂质的多晶硅层,形成覆盖第一区域中的多晶硅层并留下掩模的掩模图案来制造双多晶硅栅极。在第二区域中的多晶硅层中,将第二导电类型的杂质注入到第二区域中被掩模图案暴露的第二多晶硅层中。去除掩模图案,并对多晶硅层进行构图,以在第一区域中形成第一多晶硅图案,并在第二区域中形成第二多晶硅图案。第二多晶硅图案形成为具有从其侧壁横向突出的突起。随后,将第二导电类型的杂质注入到第二区域中的衬底中以及第二多晶硅图案的突起中。

著录项

  • 公开/公告号US8470664B2

    专利类型

  • 公开/公告日2013-06-25

    原文格式PDF

  • 申请/专利权人 KYONG BONG ROUH;YONG SEOK EUN;

    申请/专利号US201213365462

  • 发明设计人 KYONG BONG ROUH;YONG SEOK EUN;

    申请日2012-02-03

  • 分类号H01L31/8238;H01L21/84;H01L21/8234;

  • 国家 US

  • 入库时间 2022-08-21 16:46:06

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