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Delay locked loop circuit including delay line with reduced sensitivity to variation in PVT
Delay locked loop circuit including delay line with reduced sensitivity to variation in PVT
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机译:延迟锁定环路电路,包括延迟线,对PVT变化的敏感性降低
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摘要
A delay locked loop circuit is disclosed. The circuit includes a phase detector for comparing the phase of an input clock signal with the phase of a feedback clock signal that is fed back into the phase detector, and for outputting a detection signal. The circuit also includes a control circuit unit for controlling a delay line in response to the detection signal, a delay line for delaying the input clock by a predetermined amount of delay in response to output impedance calibration codes applied to the delay line, and a replica circuit configured to have the same delay conditions as those of an actual clock path to a circuit of the semiconductor device, to receive a delay clock signal of the delay line, and to generate the feedback clock signal.
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